The present invention relates to a semiconductor memory device and specifically to a data writing method.
A conventional SRAM circuit is shown in FIG. 8. In FIG. 8, a large number of memory cells 100 are arranged in an array of rows and columns (only two cells are shown in FIG. 8). Each memory cell 100 is connected to a word line WL and a pair of bit lines (BIT, NBIT). Each memory cell 100 includes, as shown in FIG. 7, two load transistors MP1 and MP2 connected to predetermined power supply VDD, two drive transistors MN1 and MN2 connected to ground power supply VSS, and two transfer transistors MN3 and MN4. The gates of the two transfer transistors MN3 and MN4 are connected to the word line WL. The drains of the transfer transistors MN3 and MN4 are connected to the bit line pair (BIT, NBIT). The bit line pair (BIT, NBIT) is connected to a sense amplifier 800, which receives an enable signal SAE, through a column selector 801, which receives a select signal CA, and a pair of signal lines SO and NSO as shown in FIG. 8.
In the SRAM having such a structure, at the time of reading data, a word line WL which is connected to a memory cell 100 to be accessed is activated, the electrical potential is discharged from one of the pair of bit lines (BIT, NBIT) which are precharged to a predetermined potential when on standby, so that a minute potential difference is caused between the bit lines BIT and NBIT. This minute amplitude signal is amplified by the sense amplifier 800 through a column selector 801, and the amplified signal is output.
However, along with a decrease in the power supply voltage which is required by finer designs of elements and wirings, the potential difference of the minute amplitude signal which activates the sense amplifier 800 has had a larger ratio with respect to the power supply voltage. Thus, it has become more difficult to shorten a time interval between activation of the word line WL and activation of the sense amplifier 800.
For example, Joel Silberman et al., “A 1.6 ns Access, 1 GHz Two-Way Set-Predicted and Sum-Indexed 64-kByte Data Cache”, 2000 Symposium on VLSI Circuits Digest of Technical Paper pp.220-221, proposes a structure shown in FIG. 9 which overcomes the above-described problems. In the structure of this document, 8 memory cells 900 (only two cells are shown in FIG. 9) are connected to a single read bit line RBIT, and this read bit line RBIT is connected to a global bit line RGBIT through a read section 910 which is formed by an NAND circuit ND and one N-type transistor N1. Thus, at the time of reading data, the time required for the bit line precharged at a predetermined potential to reach 0 V is shortened because the number of memory cells 900 connected to the read bit line RBIT is 8. Accordingly, the operation speed in a low-voltage condition is fast as compared with the SRAM having the structure of FIG. 8.
However, at the time of writing data, it is necessary to forcibly change the potential of one of the pair of bit lines (BIT, NBIT) to 0 V. If a write bit line WBIT is not provided in the semiconductor memory device of FIG. 9, the read bit line RBIT and the global bit line RGBIT are undesirably activated during the write operation, and as a result, data to be read is destroyed. In view of such, in the semiconductor memory device of FIG. 9, it is necessary to provide a write bit line WBIT independently of the read bit line RBIT. As shown in FIG. 9, the memory cell 900 is formed by 7 transistors, which include write access transistors MN3 and MN4 and a read access transistor MN5. Each transistor is connected to a pair of write bit lines WBIT and NWBIT and the read bit line RBIT. With such a structure, writing of data in the memory cell 900 is possible.
However, in the semiconductor memory device shown in FIG. 9, the number of transistors included in each memory cell 900 is 7, which is larger than that of a common memory cell of a 6-transistor structure, and accordingly, the memory area is larger than that of the 6-transistor structure.